Faculty Details
| Name | Dr.Jithin Kumar.M.V |
| Designation | Associate Professor & HOD |
| Department | Electronics & Communication Engineering |
| Qualification | BE, ME, PhD |
| hodec@hcet.in | |
| Area of Interest | Low Power VLSI, ASIC |
| Publications | Publications: 13 INTERNATIONAL JOURNALS 1. Jithin Kumar, MV & Jayanthi, KB 2015, ‘A Low-Power Hybrid Multiplication Technique for Higher Radix Hard Multiples Suppression’, Indian Journal of Science & Technology, vol. 8, no. 13. 2. Jithin Kumar, MV & Jayanthi, KB 2015, ‘Design & Analysis of A low-power Hybrid Multiplier using Modified Booth Encoder’, International Journal of Applied Engineering Research, vol. 10, no. 2, pp. 2116-2120. 3. Jithin Kumar, MV & Jayanthi, KB 2014, ‘Mathematical Modelling and Implementation of a Low-power Higher-Radix Hybrid Multiplier’, International Journal of Advanced Research Trends in Engineering and Technology, vol. 1, no. 11, pp. 23-29. 4. Jithin Kumar, MV & Jayanthi, KB 2013, ‘A Well-Configured 3-bit & 4-bit Hybrid Modified Booth Multiplier’, International Journal of Advanced Research in Biology, Engineering, Science and Technology, vol. 1, no. 5, pp. 21-24. INTERNATIONAL CONFERENCE 1. Arun Babu, Dr. Kudakwashe Dube, Prof. Subhas Mukhopadhyay, Hemant Ghayvat and Jithin Kumar M.V., Accelerometer Based Human Activities and Posture Recognition’ Proceedings of the IEEE International Conference on Data Mining and Advanced Computing (SAPIENCE-16,), 16th to 18th March 2016, Sree Narayana Gurukulam College of Engineering, Ernakulam, Kerala, India. 2. Jithin Kumar, MV & Jayanthi, KB, ‘A Well Configured Low-Power 0.25µm CMOS Re-Modified Booth Multiplier’, Proceedings of the two-day International Conference on Optoelectronics, Information and Communication Technologies (ICOICT) 2009, pp. 126-131. 3. Priyadarshini, Jithin Kumar, MV & Rajasekaren, C 2011, ‘A Novel VLSI Architecture with Reduced Hard Multiple based on Higher Radix Modified Booth Algorithm, Proceedings of the International Conference on VLSI, Communication and Networks 2011 (VCAN-2011), IET, Alwar (Rajasthan), pp. 9-13. NATIONAL CONFERENCE 1. Design & Analysis of Switching Power Reduction in a High Speed/Low Power Multiplier With a Well Configured Hybrid Technique (NCEIS 2010), Department of Electrical Engineering, Govt. College of Technology, Coimbatore - 13 (Date: 19th of March 2010) 2. A Mathematical Verification & Design of a Low-power/High-Speed Multiplier (MiNDSS 2010) Dept. of ECE, Muthayammal Engineering College, Rasipuram - 637 408 (Date: 22 & 23 of Jan 2010) 3. Design and Analysis of CMOS Voltage Controlled Oscillator. (NACC’09) Dept. of ECE, Paavai Engg. College, Pachal, Namakkal. (Date: 02nd of April 2009) 4. An effective spurious power suppression technique & it’s application on a low-power multiplier (ESIC’2008), Dept. of ECE, PSNA College of Engg. and Tech., Dindigul (Date: 01st of March 2008) 5. A Modified booth algorithm with an irrational switching power moderation technique (Third NCICC’08), Dept. of ECE, SNS College of Technology, Coimbatore (Date: 21st of Feb 2008) 6. An Illogical Switching Power Clampdown Technique for a Low-Power Multiplier (First MKCE-CONFLUENCE’08) Dept. of ECE, M. Kumarasamy College of Engg, Karur - 639 113 (Date: 02nd of Feb 2008) |
